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1 ? fn9186.2 isl6173 dual low voltage hot swap controller this ic targets dual voltage hot swap applications across the +2.5v to +3.3v (nominal) bias supply voltage range with a second lower voltage rail down to less than 1v. it features a charge pump for driving external n-channel mosfets, regulated current protection an d duration, output undervoltage monitoring and reporting, optional latch-off or retry response, and adjustable soft-start. the current regulation level (cr) for each rail is set by two external resistors and each cr duration is set by an external capacitor on the tim pin. after the cr duration has expired the ic then quickly pulls down the associated gate(s) output turning off its external fet(s). the isl6173 offers a latched output or indefinite auto retry mode of operation. pinout isl6173 (28 lead qfn) top view features ? fast current regulation amplifier quickly responds to overcurrent fault conditions ? less than 1s response time to dead short ? programmable current regulation level and duration ? two levels of overcurrent detection provide fast response to varying fault conditions ? overcurrent circuit breaker and fault isolation functions ? adjustable current regulation threshold as low as 20mv ? selectable latch-off or auto retry response to fault conditions ? adjustable voltage ramp-up for in-rush protection during turn-on ? rail independent control, monitoring and reporting i/o ? dual supply hot swap power distribution control to <1v ? charge pump allows the use of n-channel mosfets ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free available (rohs compliant) applications ? power supply sequencing, distribution and control ? hot swap/electronic breaker circuits ordering information part number temp. range (c) package pkg. dwg. # isl6173drza * 0 to +85 28 ld 5x5 qfn (pb-free) l28.5x5 ISL6173DRZA-T * 0 to +85 28 ld 5x5 qfn (pb-free) l28.5x5 isl6173eval3 evaluation platform *intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 rtr /ltch gnd pgnd cpq- bias cpq+ cpvdd vs1 uv1 en1 ocref en2 uv2 vs2 sns2 vo2 ss2 gt2 flt2 pg2 ct2 sns1 vo1 ss1 gt1 flt1 pg1 ct1 v1(in) v2(in) v1(out) v2(out) rsns1 rsns2 rset1 rset2 figure 1. typical application isl6173 en1 en2 rtr /ltch bias cpq+ cpq- cpvdd pgnd gnd ct1 ct2 vs2 sns2 gt2 vo2 uv2 pg2 flt2 flt1 pg1 ss1 ss2 ocref gt1 vo1 uv1 vs1 sns1 data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004-2005. all rights reserved all other trademarks mentioned are the property of their respective owners. february 15, 2005
2 fn9186.2 february 15, 2005 block diagram figure 2. isl6173 - internal block-diagram of the ic - channel one only q rsn s 3k 10k 10k x2 ch arg e pump x2 ch arg e pump rset cu rren t mi rror por and bandgap 633mv 1. 178v 10v(out) 1. 178v 4 iref ir e f 633mv 1. 178v load flt1 pg1 ct 1 ss1 uv1 ocref en1 rt r/ l t ch cpq+ cpq- cpvdd bi as vs1 sns1 gt1 vo1 pgnd gnd bi as bi as 10v cpvdd cpvdd oc timer & logic soft start amplifier cu rren t limit amplifier 24a 10a 10a woc co mp arato r oc co mp arato r - - + + + + - - + + - - timeout co mp arato r uv co mp arato r io i set isl6173 vin vo rref cp cv css rs1 rs2 ct 42a isl6173
3 fn9186.2 february 15, 2005 pinout 28 lead qfn top view 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 rtr /ltch gnd pgnd cpq- bias cpq+ cpvdd vs1 uv1 en1 ocref en2 uv2 vs2 sns2 vo2 ss2 gt2 flt2 pg2 ct2 sns1 vo1 ss1 gt1 flt1 pg1 ct1 pin descriptions pin name function description 1 sns1 current sense input this pin is c onnected to the current sense resistor and control mosfet drain node. it provides current sense signal to the internal comparat or and amplifier in conjunction with vs1 pin. 2 vo1 output voltage 1 this pin is connected to the control mosfet switch source, which connects to a load. internally, this voltage is used for ss control. 3 ss1 soft-start duration set input a capacitor from this pin to ground sets the output soft-start ramp slope. this capacitor is charged by the internal 10a current source setting the soft -start ramp. the output voltage ramp tracks the ss ramp by controlled enhancement of fet gate. once ramp-up is completed, the capacitor continues to charge to the cpvdd voltage rail. if common capacitor is used (by tying ss1, ss2 together and the capacitor to gnd from the connection) then bot h the outputs track each other as they ramp up. 4 gt1 gate drive output direct connection to the gate of the exter nal n-channel mosfet. at turn-on the gate will charge to 4 x vbias or 10v(max) from the 24a source. 5flt1 fault output this is an open drain output. it asserts (pul ls low) once the current regulation duration (determined by the ctx timeout cap) has expired. this output is valid for vbias>1v. 6pg1 power good output this is an active low, open drain output. w hen asserted (logic zero), it indicates that the voltage on uv1 pin is more than 643mv (633mv + 10mv hysteresis). this output is valid at vbias >1v. 7 ct1 timer capacitor a capacitor from this pin to ground contro ls the current regulation duration from the onset of current regulation to channel shutdown (current limit ti me-out). once the voltage on ctx cap reaches v ct_vth the gate output is pulled down and the flt is asserted. the duration of current limit time-out = (c tim *1.178)/10a when the oc comparator trips and the rtr /ltch pin is pulled low, the ic?s faulty channel remains shut down for 64 cycles (each cy cle length is equal to the current limit time-out duration). 8rtr / ltch retry or latch input this input dictates the ic behavior (for either channel) under oc condition. if it is pulled high (or left floating), the ic will shut down upon oc time-out. if it is pulled low, the ic will go into retry mode after an interval determined by the capacitor on ctx pin. the faulting channel will remain shut down for 64 cycles and will try to come out of it on the 65t h cycle. each cycle l ength is determined by the formula shown in ct pin description. 9 gnd chip gnd this pin is also internally shorted to the metal tab at the bottom of the ic. 10 pgnd charge pump ground. both gnd and pgnd must be tied together externally. isl6173
4 fn9186.2 february 15, 2005 11 cpq- charge pump capacitor low side flying cap lowside. 12 bias chip bias voltage provides ic bias. should be 2v to 4v for ic to function normally. this pin can be powered from a supply voltage that is not being controlled. it is preferable to use 3.3v even if the channels being controlled are 2.5v or lower because more gate drive voltage will be available to the mosfets. 13 cpq+ charge pump capacitor high side flying cap highside. use of 0.1f for 2.5v bias and 0.022f for 3.3v bias is recommended. 14 cpvdd charge pump output this is the voltage used for some internal pullups and bias. use of 0.47f (minimum) is recommended. 15 ct2 timer capacitor same function as pin 7 16 pg2 power good output same function as pin 6 17 flt2 fault output same as pin 5 18 gt2 gate drive output same as pin 4 19 ss2 soft-start duration set input same as pin 3 20 vo2 output voltage 2 same as pin 2 21 sns2 current sense input same as pin 1 22 vs2 current sense reference voltage input for one of the two voltages. provides a 20a current source for the iset series resistor which sets the voltage to which the sense resistor ir drop is compared. 23 uv2 undervoltage monitor input this pin is one of the two inputs to the undervoltage comparator. the other input is the 633mv reference. it is meant to sense the output volt age through a resistor divider. if the output voltage drops so that the voltage on the uv pin goes below 633mv, pg2 is deasserted. 24 en2 enable this is an active low input. when asserted ( pulled low), the ss and gate drive are released and the output voltage gets enabled. when deasserted (pull ed high or left floating), the reverse happens. 25 ocref ref. current adj. allows adjustment of the reference current through r set and the internal current regulation set resistor, thus setting the thresholds for cr, oc and woc. 26 en1 enable input same as pin 24 27 uv1 undervoltage monitor input same as pin 23 28 vs1 current sense reference same as pin 22 pin descriptions (continued) pin name function description isl6173
5 fn9186.2 february 15, 2005 absolute maximum rati ngs thermal information vbias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5v gtx, cpq+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +12v enx , rtr /ltch, snsx, pgx , fltx, vsx, ctx, uvx, ssx, cpq-, cpvdd. . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5vdc output current . . . . . . . . . . . . . . . . . . . . . . . short circuit protected esd rating human body model (per mil-std-883 method 3015.7) . . .1750v machine model (per eiaj ed-4701 method c-111) . . . . . . . .125v charged device model (per eos/esd ds5.3, 4/14/93) . . .1750v operating conditions vbias/vin1 supply voltage range. . . . . . . . . . . . +2.25v to +3.63v temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . . 0c to 85c thermal resistance (typical, notes 1, 4) ja (c/w) jc (c/w) 5x5 qfn package . . . . . . . . . . . . . . . . 42 12.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c for recommended soldering conditions, see tech brief tb389. (qfn - leads only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. all voltages are relative to gnd, unless otherwise specified. 3. 1v (min) on the bias pin required for flt to be valid. 4. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v dd = 2.5v to +3.3v, t a = t j = 0c - 85c, unless otherwise specified. parameter symbol test conditions min typ max unit current regulation control current regulation threshold voltage v crvth_1 riset = 1.25k 1%, i set = 20a202530mv current regulation accuracy v crvth_1 r riset = 1.25k 1%, i set = 20a -20 +20 % current regulation threshold voltage v crvth_2 riset = 2.50k 1%, i set = 20a455055mv current regulation accuracy v crvth_2 r riset = 2.50k 1%, i set = 20a -10 +10 % ct threshold voltage v ct_vth 1.128 1.178 1.202 v ct charging current i ct 10 a gate drive gate response time from woc (open) pd_woc_open gate open 100mv of overdrive on the woc comparator 3ns gate response time from woc (loaded) pd_woc_load gate = 1nf 100 ns gate response time in current regulation mode (loaded) pd_cr_load gate = 1nf 120% load current 5s gate turn-on current igate gate = 2v v vs = 2v v sns = 2.1v 21 24 27 a gate voltage v gate bias = 2.5v (see graph on page 7) 7.5 9.0 v 2.1 < bias < 2.5 (see graph on page 7) 8v bias supply current i bias v bias = 3.3v 9 17 ma por rising threshold vin_por_l2h 2.12 v por falling threshold vin_por_h2l 2.10 v por threshold hysteresis vin_por_hys 5 mv isl6173
6 fn9186.2 february 15, 2005 i/o undervoltage comparator falling threshold v uv_vthf 620 635 650 mv undervoltage comparator hysteresis v uv_hyst 71625mv en rising threshold pwr_vth_r v bias = 2.5v 1.55 1.95 2.19 v en falling threshold pwr_vth_f v bias = 2.5v 0.97 1.10 1.30 v en hysteresis pwr_hyst v bias = 2.5v 600 850 1100 mv pg pull-down voltage vol_pg i pg = 8ma 0.047 0.4 v flt pull-down voltage (note 3) vol_flt i flt = 8ma 0.047 0.4 v soft-start charging current iq_ss vss = 1v 10 a charge pump cpvdd v_cpvdd v bias = 3.3v 4.9 5.2 5.5 v cpvdd v_cpvdd v bias = 3.3v t = 25c external user load = 6ma 5.0 v electrical specifications v dd = 2.5v to +3.3v, t a = t j = 0c - 85c, unless otherwise specified. (continued) parameter symbol test conditions min typ max unit isl6173
7 fn9186.2 february 15, 2005 typical performance curves (at 25c unless otherwise specified) figure 3. i_bias vs v_bias figure 4. por rising threshold vs temperature figure 5. v gate vs v_bias figure 6. v gate vs v_bias figure 7. gate drive vs temperature figure 8. pg_vol vs temperature 0 2 4 6 8 10 12 1.0 1.4 1.7 2.0 2.3 2.9 3.2 3.7 v_bias(v) i_bias (ma) c pq = 22nf, c pvdd = 0.47f 2 2.005 2.01 2.015 2.02 2.025 2.03 2.035 2.04 2.045 -10 0 25 40 60 85 temperature (c) por rising (v) 0 1 2 3 4 5 6 7 8 9 10 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.5 3.7 3.8 3.9 4 v_bias (v) v gate (v) c pq = 22nf, c pvdd = 0.47f 0 1 2 3 4 5 6 7 8 9 10 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.5 3.7 3.8 3.9 4 v_bias (v) v gate (v) c pq = 0.1f, c pvdd = 0.47f 23.4 23.6 23.8 24 24.2 24.4 24.6 -10 0 25 40 60 85 i g (a) temperature (c) 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 pg_vol -10 0 25 40 60 85 temperature (c) i pg = 8ma isl6173
8 fn9186.2 february 15, 2005 figure 9. woc response vs load capacitance figure 10. response time vs i o *r sns figure 11. por falling vs temperature typical performance curves (at 25c unless otherwise specified) (continued) 1 10 100 1000 10000 c g (nf) t response (ns) 0 0.1 0.47 1 4 8.7 14 22 2 0 0.5 1 1.5 2 2.5 3 100 150 200 250 300 oc (% of limit) response time (s) 1.996 1.998 2 2.002 2.004 2.006 2.008 por falling (v) -10 0 25 40 60 85 temperature (c) isl6173
9 fn9186.2 february 15, 2005 detailed description of operation isl6173 targets dual voltage hot-swap applications with a bias of 2.1v to 3.6vdc an d the voltages being controlled down to 0.7vdc. the ic?s main function is to limit and regulate the inrush current into the loads. this is achieved by enhancing an external mosfet in a controlled manner. in order to fully enhance the mosfet, the ic must provide adequate gate to source voltage, which is typically 5v or greater. hence, the final steady-state voltage on gate (gt) pin must be 5v above the load voltage. two internal charge- pumps allow this to happen. controlled soft-start the output voltages are monitor ed through the vo pins and slew up at a rate determined by the capacitors on the soft- start (ss) pin, as illustrated in figure 12. 24a of gate charge current is available. t he soft-start amplifier controls the output voltage by robbin g some of the gate charge current thus slowing down the mosfet enhancement. when the load voltage reaches its set level, as sensed by its respective uv pin through an external resistor divider, the power good (pg ) output goes active. current monitoring and protection the ic monitors the load current (io) by sensing the voltage- drop across the low value current sense resistor (r sns ), which is connected in series with the mosfet as shown in the diagram on page 2, through sense (sns) and voltage set (vs) pins. the latter is through a resistor, r set , as shown. two levels of overcurrent detection are available to protect against all possible fault scenarios. these levels are: 1. current limit or current regulation (cr) 2. way overcurrent (woc) each of these modes is described in detail as follows: 1. current limit or current regulation (cr) mode: - when the load current reaches the cu rrent regulation threshold, the current amplifier loop closes and the circuit behaves like a current source. the current limit amplifier is a folded cascode type with source follower output capable of pulling down the gate very fast in response to fast overload transients. the current regulation threshold is set by setting a reference current, i set , through r set by selecting an appropriate resistor between ocref and gnd, which sets i ref . the relationship between i ref and i set is i ref = 4*i set , where i ref = vocref/rocref = 1.178/rocref. i ref would typically be set at 80a. selecting appropriate values for r set and r sns such that when i o = i cr , the operating mode is shown in figure 13. when the circuit enters this mode, the oc comparator detects it and sets off the timer. ct begins to charge from an internal 10a current source. the amount of time it takes for this cap to charge to 1.178v sets up the current regulation duration. upon expiration of this time-out period, the mosfet gate is pulled down quickly by the current limit amplifier, unless the load current level had already dropped back to a level below the current regulation threshold level prior to that. in that case, the current regulation mode is no longer active, the mosfet is allowed to fully enhance and the ic discharges the c t cap. if rtr /ltch pin is left open or pulled to bias, the output remains latched off after the expiration of the time-out period determined by c t . if rtr /ltch pin is pulled to gnd, the ic q ss1 g t 1 v o 1 10v cpvdd soft- start amplifier 24a 10a + 42a vo 0 0 vin cpvdd vin + - - figure 12. soft-start operation (eq. 1) io*r sns = i set *r set q rsns 3k rset 4 iref vs1 sns1 gt1 10v current limit amplifier 24a - + iset vin vo + - + - isl6173 current regulation iset*rset = io*rsns figure 13. current regulation operation mode: isl6173
10 fn9186.2 february 15, 2005 automatically retries to turn on the mosfet after a wait period, during which c t is charged and discharged 64 times and the retry attempt takes place on the 65th time. this wait period allows the mosfet junction to cool down. 2. way overcurrent (woc) mode - this mode is designed to handle very fast, very low impedance shorts on the load side, which can result in very high di/dt. typically, the current limit set for this mode is 300% of the current regulation limit. this mode uses a very fast co mparator, which directly looks at the voltage drop across r sns and pulls the gate very quickly to gnd (as shown in figure 14) and immediately releases it. if the woc is still present, the ic enters current regulation mode and the rest of the current regulation behavior follows as described earlier in undercurrent regulation mode. additionally, as shown in the block diagram, there is also an ?oc comparator?, which also looks at the rsense voltage drop. when this drop exceeds the current limit set point, it triggers the timeout circuit, which starts ticking and ctx is allowed to charge. if the current limit condition remains in effect until after the time-out period expires (ctx voltage exceeding 1.178v), the gate of the mosfet is pulled down, the ssx capacitor is discharged, flt is asserted and a new ss sequence is allowed to begin after enx recycle or by keeping the rtr /ltch pin pulled low. the voltage on ocref pin is the same as the internal band- gap reference voltage, which is 1.178v (nominal). a resistor to gnd from this pin sets the reference current (and hence the reference voltage) for th e current limit amplifier and oc/woc comparators. the current regulation (cr) duration is set by the capacitor on ct pin to gnd. once the voltage on this pin reaches 1.178v, the cr duration expires. fault (flt ) pin goes active (pulls low), signaling the load of a fault condition and the gate (gt) pin gets pulled low. retry vs latched fault operational modes: rtr /ltch pin dictates the ic behavior after the gate (gt) pin pulls down following oc timeout expiration. if the rtr /ltch pin is left floating, the gate pin will remain latched off. it can only be released by de-asserting and reasserting the enable (en ) input. if rtr /ltch pin is pulled to gnd, then the retry mode will be activated. in this mode the ic will automatically attempt to turn-on the mosfet after a delay, determined by the capacitor on ct pin. in the retry mode, the internal logic charges and discharges the ct cap 64 times during ?wait? period. on the 65th time, the flt output clears during retry attempt. if the overcurrent condition persists after the soft-start, the ct pin will again start charging and the process repeats. bias and charge pump voltages: the bias pin feeds the chip bias voltage directly to the first of the two internal charge pumps, which are cascaded. the output of the first charge pump, in addition to feeding the second charge pump, is accessible on the cpvdd pin. the voltage on the cpvdd pin is approximately 5v. it also provides power to the por an d band-gap circuitry as shown in the block diagram. a capacitor connected externally across cpq+ and cpq- pins of the ic is the ?flying? cap for the charge-pump. the second charge-pump is used exclusively to drive the gates of the mosfets through the 24a current sources, one for each channel. the output of this charge pump is approximately 10v as shown in the block diagram. tracking q rsns 3k rset vs1 sns1 gt1 - + io iset vin vo + - + - isl6173 25 ? woc comparator gate pulldown current figure 14. woc operation ch1: v o 1, ch2: v o 2, t = 2ms/div, c ss = 0.066f figure 15. tracking mode waveforms isl6173
11 fn9186.2 february 15, 2005 the two channels can be forced to track each other by simply tying their ss pins together and using a common ss capacitor. in addition, their en pins also must be tied together. typical start-up waveforms in this mode are shown in figure 15. if one channel goes down for any reason, the other one will too. o ne important thing to note here is that only the overcurrent latch-off mode will work. auto-retry feature will not work. retry must be controlled manually through en . typical hot-plug power up sequence 1. when power is applied to the ic on the bias pin, the first charge pump immediately powers up. 2. if the bias voltage is 2.1v or higher, the ic comes out of por. both ss and ct caps remain discharged and the gate (gt) voltage remains low. 3. enx pin, when pulled low (below it?s specified threshold), enables the respective channel. 4. ssx cap begins to charge up through the internal 10a current source, the gate (gt) voltage begins to rise and the corresponding output voltage begins to rise at the same rate as the ss cap voltage. this is tightly controlled by the soft-start amplifier shown in the block diagram. 5. ss cap begins to charge but the corresponding ctx cap is held discharged. 6. fault (flt ) remains deasserted (stays high) and the output voltage continues to rise. 7. if the load current on the output exceeds the set current limit for greater than the oc timeout period, flt gets asserted and the channel shutdown occurs. 8. if the voltage on uv pin exceeds 633mv threshold as a result of rising vo, the power good (pg ) output goes active. 9. at the end of the ss interval, the ss cap voltage reaches cpvdd and remains charged as long as en remains asserted or there is no other fault condition present that would attempt to pull down the gate. state diagram this is shown in figure 16. it provides a quick overview of the ic operation and can also be used as a troubleshooting road map. isl6173
12 fn9186.2 february 15, 2005 ic operation state diagram sof t start (tss) res et & latch of f state flt asserted current limit mod e run oc timer (toc) output voltage available pg asserted gate pulldow n no po w e r pg & flt outputs valid flt cleared apply pow er bias>1v bias>2v en a s s e r t e d en de - a s s e r t e d rtr/ltch = l rtr/ltch = h io>i cr (woc) count 64 pu l s e s & res et vuv>645mv vuv<633mv io>i cr io>>i cr io>=ic r and t>toc figure 16. isl6173
13 fn9186.2 february 15, 2005 applications information selection of exte rnal components the typical application circuit of figure 2 has been used for this section, which provides guidelines to select the external component values. mosfet (q1) this component should be selected on the basis of its r ds(on) specification at the expe cted vgs (gate to source voltage) and the effective input gate capacitance (ciss). one needs to ensure that the combined voltage drop across the rsense and r ds(on) at the desired maximum current (including transients) will still keep the output voltage above the minimum required level. power dissipation in the device under short circuit condition should also be an important consideration especially in auto-retry mode (rtr /ltch pin pulled low). using isl6173 in latched off mode results in lower power dissipation in the mosfet. ciss of the mosfet influences the overcurrent response time. it is recommended that a mosfet with ciss of less than 10nf be chosen. ciss will also have an impact on the ss cap value selection as seen later. current sense resistor (r sns ) the voltage drop across this resistor, which represents the load current (io), is compared against the set threshold of the current regulation amplifier. the value of this resistor is determined by how much combined voltage drop is tolerable between the source and the load. it is recommended that at least 20mv drop be allowed across this resistor at max load current. this resistor is expec ted to carry maximum full load current indefinitely. hence, the power rating of this resistor must be greater than i o(max) 2 *r sns . this resistor is typically a low value resistor and hence the voltage signal appearing across it is also small. in order to maintain high current sense accuracy, current sense trace routing is critical. it is reco mmended that either a four wire resistor or the following routing method be used: current set resistor (r set) this resistor directly sets the threshold for the current regulation amplifier and indirectly sets the same for the oc and woc comparators in conjunction with r sns . once r sns has been selected, use equation 1 (on page 9) to calculate r set . use 20a for i set in a typical application. reference current set resistor (r ref ) this resistor sets up the current in the internal current source, i ref /4, shown in figure 2 for the comparators. the voltage at the ocref pin is the same as the internal bandgap reference. the current (i ref ) flowing through this resistor is simply: i ref = 1.178/r ref this current, i ref , should be set at 80a to force 20a in the internal current source as show n in figure 2, because of the 4:1 current mirror. this equates to the resistor value of 14.7k. selection of rs1 and rs2 these resistors set the uv detect point. the uv comparator detects the undervoltage condition when it sees the voltage at uv pin drop below 0.633v. the resistor divider values should be selected accordingly. charge pump capa citor selection (c p and c v ) c p is the ?flying cap? and c v is the smoothing cap of the charge pump, which operates at 450khz set internally. the output resistance of the charge pump, which affects the regulation, is dependent on the c p value and its esr, charge-pump switch resistance, and the frequency and esr of the smoothing cap, c v . it is recommended that c p be kept within 0.022f (minimum) to 0.1f (maximu m) range. only ceramic capacitors are recommended. use 0.1f cap if cpvdd output is expected to power an external circuit, in which case the current draw from cpvdd must be kept below 10ma. c v should at least be 0.47f (ceramic only). higher values may be used if low ripple performance is desired. time-out capacitor selection (c t ) this capacitor controls the current regulation time-out period. as shown in figure 2, when the voltage across this capacitor exceeds 1.178v, the ti me-out comparator detects it and pulls down the gate voltage thus shutting down the channel. an internal 10a current source charges this capacitor. hence, the value of this capacitor is determined by the following equation: c t = (10a * t out )/1.178 where, t out = desired time-out period. load current carrying traces r sns current sense traces figure 17. recommended current sense resistor pcb layout isl6173
14 fn9186.2 february 15, 2005 soft-start capacitor selection (c ss ) the rate of change of voltage (dv/dt) on this capacitor, which is determined by the internal 10a current source, is the same as that on the output load capacitance. hence, the value of this capacitor directly controls the inrush current amplitude during hot swap operation. c ss = c o *(10a/i inrush ) where, c o = load capacitance i inrush = desired inrush current i inrush is the sum of the dc steady-state load current and the load capacitance charging cu rrent. if the dc steady-state load remains disabled until after the soft-start period expires (pgx could be used as a load enable signal, for example), then only the capacitor charging current should be used as i inrush . the css value should always be more than (1/2.4) of that of ciss of the mosfet to ensure proper soft-start operation. this is because the ciss is charged from 24a current source whereas the css gets charged from a 10a current source (please refer to figure 12). in order to make sure both vss and vo track during the soft-start, this condition is necessary. isl6173 evaluation platform the isl6173eval1 is the primary evaluation board for this ic. the board is a standalone evaluation platform and it only needs input bias and test voltages. the schematic for this board is shown in figures 20 and 21. the component placement diagram is shown in figure 22. the evaluation board has been designed with a typical application and accessibility to all the features in mind to enable a user to understand and verify these features of the ic. the circuit is designed for 2a for each input rail but it can easily be scaled up or down by adjusting some component values. led indicators are provided to indicate fault and power good status. switches are there to perform enable function for each channel, to select auto-retry or latchoff mode and to check woc and cr modes. there are two input voltages, one for each channel plus there is ?+5v? input. the latter is to test the pull-up capability of flt and pg outputs to +5v and also to power the leds and the dynamic load circuitry. isl6173 does not require 5v. pins ss1 and ss2 of the ic are available on header j2 as test points so that they can be tied together to achieve tracking between vo1 and vo2. both the enable (en ) switches (sw1 and sw2) must be turned on to check this function. each channel is preloaded with capacitive load. extra load can be externally applied as required. the outputs are brought out to banana sockets to allow external loading if desired. j1 and j3 are wire jumpers. a user can replace them with wire loops to attach a scope current probe. however, doing so may reduce the di/dt enough to prevent woc comparator from tripping. the internal current regulation amplifier is fast enough to respond to very fast di/dt. hence, it is advisable to use the on board dynamic load circuitry, as will be described, if a user wants to check the woc performance. the dynamic load circuitry, shown in figure 21, is included on the board on both channels to ensure minimum inductance in the current flow path. two sets of load are available per output: 1) cr load: this load is set at 1 ? (approximately 3.3a for 3.3v output), which is higher than the 2.2a of cr limit but less than woc limit (6.6a) set on the board. 2) woc load: this load is set at 340m ? , which is roughly 10a for 3.3v supply. this is higher than 6.6a woc limit set on the board. a function/pulse generator is required to activate the dynamic load circuitry. the f unction/pulse generator should have adjustable pulse-width (3ms), single pulse (manual trigger) and 5v pulse amplitude capability. agilent model no: 33220a or equivalent is a good choice. the function generator needs to be connected through a co-ax cable to j11 or j12 for channel 1 or channel 2 respectively. woc or cr load can be activated by turning sw4 or sw5 (channel 1) and sw6 or sw7 (channel 2) on followed by applying the pulse generator to turn on an appropriate load. the load circuit consists of a mosfet driver (el7202), mosfet (irf7821) and surface mount load resistors. the mosfet drivers, u2 and u3, respond to a pulse from the generator to turn on the mosfet for the duration of the pulse, which should be set less than the timeout period described in ?time-out capacitor selection?. on this board the timeout capacitor value is 0.15f, which corresponds to a timeout period of 17.67ms. one way to tell if the woc mode is active would be by looking at the gate waveform of the control mosfet (m1 or m2). the woc comparator when tripped, pulls down the gate hard. the following waveform shows woc operation: isl6173
15 fn9186.2 february 15, 2005 channel 1 is vgate, channel 2 is the pulse generator output and channel 3 is vout. note how vgate gets immediately pulled down to zero volts up on load application. in cr mode, however, vgat e always remains above zero volts because woc comparator never trips. this can be seen on the following scope shot: it is also important to note that in woc mode, although vgate gets pulled down to zero initially, the gate is quickly released and slowly rises until the cr am plifier takes control. figure 18. woc operation figure 19. current regulation operation isl6173
16 fn9186.2 february 15, 2005 bill of materials fo r isl6173 eval 1 board item qty reference part pkg mfg p/n manufacturer 1 2 c1, c18 220f leaded upm1e221mph6 or eq nichicon 2 2 c2, c17 47f leaded upm1e470meh or eq nichicon 3 2 c3, c4 0.1f 0805 any 4 2 c5, c6 1000pf 0805 any 5 2 c9, c10 0.033f 0805 any 6 2 c11, c12 0.15f 0805 any 7 1 c13 0.47f 0805 any 8 1 c14 2.2f 1206 any 9 2 c19, c20 0.01f 0805 any 10 1 c21 10f 7343 any 11 1 c22 0.022f 0805 any 12 2 d1, d6 mbr130p sma mbr130p on semi 13 2 d3, d4 led grn 1206 pg1101w stanley 14 2 d2, d5 led red 1206 br1101w stanley 15 1 j2 2 pin header any 16 2 j1, j3 jumper any 17 2 j11, j12 bnc jack 18 6 m1, m2, m3, m4, m5, m6 irf7821 so8 irf7821 international rectifier 19 10 rs1, rs2, r10, r12, r30, r31 1k 0805 any r55, r56, r57, r58 20 6 r1, r27, r49, r50, r51, r52 0.01 2512 any 21 4 r2, r3, r25, r26 390 0805 any 22 1 r8 3.57k 0805 any 23 1 r9 2.55k 0805 any 24 1 r11 14.7k 0805 any 25 3 r14, r15, r20 0 0805 any 26 4 r16, r17, r18, r19 10k 0805 any 27 2 r29, r32 1.1k 0805 any 28 4 r33, r34, r35, r36 10 0805 any 29 6 r37, r38, r42, r43, r44, r45 1 2512 any 30 10 r39, r40, r41, r46, r47, r48 5 2512 any r61, r62, r63, r64 31 2 r53, r54 100 1206 any 32 2 r59, r60 49.9 0805 any 34 1 u1 isl6173 qfn28 5x5 isl6172 intersil 35 2 u2, u3 el7202/so so8 intersil 38 7 sw5, sw6, sw7, sw8, sw9, sw10, sw11 toggle switch gt11mcke c & k isl6173
17 fn9186.2 february 15, 2005 isl6173 schematic, isl6173 eval1 figure 20. open = latch close = retry open = disable close = enable 3.3v 2.5v pg2 flt1 flt2 no stuff no stuff gnd_in gnd_out vi_1 vi_2 vo1 vo2 5v 1 1 1 1 1 1 2 1 1 1 1 5 6 7 8 1 2 3 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 1 rtr/ltch 8 bias 12 cpq+ 13 cpq- 11 cpvdd 14 pgnd 10 gnd 9 ct1 7 ct2 15 vs2 22 sns2 21 gt2 18 vo2 20 vo1 2 gt1 4 sns1 1 vs1 28 en1 26 en2 24 uv1 27 pg1 6 flt1 5 ss1 3 pg2 16 flt2 17 ss2 19 uv2 23 ocref 25 gnd1 29 5 6 7 8 1 2 3 4 r17 10k r3 390 c21 10f sw3 r9 2.55k j9 tp2 c13 0.47f tp15 tp16 tp13 c20 0.01f j3 con2 tp7 d6 mbr130p tp18 rs2 1k j10 r18 10k r16 10k r26 390 tp11 m1 irf7821 tp14 r30 1k r11 14.7k tp3 r54 100 tp9 c22 0.022f r10 1k c5 1000pf c3 0.1f tp8 d5 led55b/to c10 0.033f j4 tp6 rs1 1k r20 0 r14 0 c18 220f r29 1.1k r31 1k c2 47f r2 390 d3 led55b/to tp5 r12 1k c4 0.1f c6 1000pf c12 0.15f c1 220f tp17 sw2 j8 c9 0.033f c14 2.2f r15 0 r1 0.01 tp12 j6 c17 47f r32 1.1k tp1 d4 led55b/to r8 3.57k r25 390 tp4 tp10 c11 0.15f j2 con2 c19 0.01f j1 con2 r19 10k j7 d2 led55b/to sw1 r53 100 j5 r27 0.01 d1 mbr130p isl6173 u1 m2 irf7821 5v 5v 5v 5v vo1 vo2 vi_1 vi_2
18 fn9186.2 february 15, 2005 schematic, isl6173 eval1 (continued) 1 tp30 r59 49.9 vo2 vo1 r60 49.9 nc8 8 outa 7 v+ 6 outb 5 in2_ 4 gnd 3 in2 2 nc1 1 u2 el7202/so 1 tp31 1 tp35 nc8 8 outa 7 v+ 6 outb 5 in2_ 4 gnd 3 in2 2 nc1 1 u3 el7202/so 1 tp36 1 tp32 5 6 7 8 1 2 3 4 m5 irf7821 r33 10 r61 5 r34 10 r35 10 r36 10 r37 1 r38 1 r39 5 r40 5 r41 5 r42 1 r43 1 r44 1 r45 1 r46 5 r47 5 r48 5 5 6 7 8 1 2 3 4 m6 irf7821 5v 5 6 7 8 1 2 3 4 m3 irf7821 5 6 7 8 1 2 3 4 m4 irf7821 r62 5 r49 01 r50 01 r51 01 1 tp19 5v r52 01 1 2 3 4 j11 1 tp20 1 2 3 4 j12 1 tp21 r63 5 1 tp22 r64 5 r55 1k 1 tp23 r56 1k r57 1k sw6 r58 1k 1 tp24 sw4 1 tp25 sw5 1 tp33 1 tp26 sw7 1 tp27 1 tp28 1 tp34 1 tp29 figure 21. isl6173
19 fn9186.2 february 15, 2005 isl6173 isl6173 eval 1 - component layout figure 22.
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9186.2 february 15, 2005 isl6173 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l28.5x5 28 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhd-1 issue i) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - 0.02 0.05 - a2 - 0.65 1.00 9 a3 0.20 ref 9 b 0.18 0.25 0.30 5,8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7,8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7,8 e 0.50 bsc - k0.20 - - - l 0.50 0.60 0.75 8 n282 nd 7 3 ne 7 3 p- -0.609 --129 rev. 1 11/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation.

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